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? semiconductor components industries, llc, 2009 january, 2009 ? rev. 9 1 publication order number: ncv8660/d ncv8660 very low i q ld0 150 ma regulator with reset and delay time select the ncv8660 is a precision very low iq low dropout voltage regulator. quiescent currents as low as 28 a typical make it ideal for automotive applications requiring low quiescent current with or without a load. integrated control features such as reset and delay time select make it ideal for powering microprocessors. it is available with a fixed output voltage of 5.0 v and 3.3 v and regulates within 2.0%. features ? fixed output voltage of 5 v and 3.3 v ? 2.0% output voltage up to v bat = 40 v ? output current up to 150 ma ? microprocessor compatible control functions: ? delay time select ? reset output ? ncv prefix for automotive ? site and change control ? aec ? q100 qualified ? low dropout voltage ? low quiescent current of 28 a typical ? stable under no load conditions ? protection features: ? thermal shutdown ? short circuit ? these are pb ? free devices applications ? automotive: ? body control module ? instrument and clusters ? occupant protection and comfort ? powertrain ? battery powered consumer electronics figure 1. application diagram dt out ro in dt out ro gnd ncv8660 c out 2.2 f c in 0.1 f v bat 13.2 v http://onsemi.com http://onsemi.com dpak 5 ? pin dt suffix case 175aa ordering information 1 5 marking diagrams 1 x = 5 for 5 v output, 3 for 3.3 v output y = 1 for 8 ms, 128 ms reset delay, = 3 for 16 ms, 64 ms reset delay a = assembly location l = wafer lot y = year ww = work week g or = pb ? free package 8660yxg alyww see detailed ordering and shipping information in the dimensions section on page 12 of this data sheet. 1 8 660yx alyww 1 8 soic ? 8 fused case 751
ncv8660 http://onsemi.com 2 pin descriptions pin symbol function dpak soic ? 8 fused 1 1 in input supply voltage. 0.1 f bypass capacitor to gnd at the ic. 2 2 r o reset output. cmos compatible output. goes low when v out drops by more than 7% from nominal. 3, tab 5 ? 8 gnd ground 4 3 dt reset delay time select. short to gnd or connect to out to select time. 5 4 out regulated voltage output. 2.2 f to ground for typical applications. figure 2. block diagram + ? in dt ro out vref1 + ? vref2 gnd current limit and thermal shutdown timing circuit
ncv8660 http://onsemi.com 3 absolute maximum ratings rating symbol min max unit input voltage (in) v in ? 0.3 40 v input current i in ? 1.0 ? ma output voltage (out) dc transient, t < 10 s (note 1) v out ? 0.3 ? 0.3 5.5 16 v output current (out) i out ? 1.0 current limited ma storage temperature range t stg ? 55 150 c dt (reset delay time select) voltage (note 2) v dt ? 0.3 16 v dt (reset delay time select) current (note 2) i dt ? 1.0 1.0 ma ro (reset output) voltage dc transient, t < 10 s v ro ? 0.3 ? 0.3 5.5 16 v ro (reset output) current i ro ? 1.0 1.0 ma esd capability esd capability, human body model (note 3) esd hb ? 2.0 2.0 kv esd capability, machine model (note 3) esd mm ? 200 200 v esd capability, charged device model (note 3) esd cdm ? 1.0 1.0 kv thermal resistance junction ? to ? case (note 4) dpak 5 r jc 15 c/w junction ? to ? ambient (note 4) dpak 5 r ja 66 c/w junction ? to ? tab (note 4) dpak 5 r jt 4.0 c/w junction ? to ? ambient (note 4) soic ? 8 fused r ja 104 c/w junction ? to ? lead (pin 6) (note 4) soic ? 8 fused r jt 33 c/w lead soldering temperature and msl moisture sensitivity level dpak 5 soic ? 8 fused msl 1 3 ? lead temperature soldering: smd style only, reflow (note 5) pb ? free part 60 ? 150 sec above 217 c, 40 sec max at peak sld ? 265 peak c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. the output voltage must not exceed the input voltage. 2. external resistor required to minimize current to less than 1 ma when the control voltage is above 16 v. 3. this device series incorporates esd protection and is tested by the following methods: esd hbm tested per aec ? q100 ? 002 (eia/jesd22 ? a114) esd mm tested per aec ? q100 ? 003 (eia/jesd22 ? a115) esd cdm tested per eia/jesd22/c101, field induced charge model 4. values represented typical steady ? state thermal performance on 1 oz. copper fr4 pcb with 1 in 2 copper area. 5. per ipc / jedec j ? std ? 020c. operating range pin symbol, parameter symbol min max unit v in , input voltage operating range v in 4.5 40 v junction temperature range t j ? 40 150 c
ncv8660 http://onsemi.com 4 electrical characteristics 5.5 v < v in < 40 v, ? 40 c t j +150 c, unless otherwise specified characteristic symbol conditions min typ max unit general quiescent current i q 100 a < i out < 150ma, v in = 13.2v, t j = 25 c ? 25 30 a 100 a < i out < 150ma, v in = 13.2v, t j 85 c ? ? 40 thermal shutdown (note 6) t sd 150 175 195 c thermal hysteresis (note 6) t hys ? 25 ? c out output voltage v out 6 v v in 16 v, 0.1 ma i out 150 ma 4.9 5.0 5.1 v 6 v v in 40 v, 0.1 ma i out 100 ma 4.9 5.0 5.1 5.6 v v in 16 v, 0 ma i out 150 ma, ? 40 c t j +125 c 4.9 5.0 5.1 output voltage v out 5.5 v v in 16 v, 0.1 ma i out 150 ma 3.234 3.3 3.366 v 5.5 v v in 40 v, 0.1 ma i out 100 ma 3.234 3.3 3.366 output current limit i cl out = 96% x v out nominal 205 ? 525 ma output current limit, short circuit i sckt out = 0 v 205 ? 525 ma load regulation v out v in = 13.2 v, i out = 0.1 ma to 150 ma ? 40 10 40 mv line regulation v out i out = 5 ma, v in = 6 v to 28 v ? 20 0 20 mv dropout voltage ? 5.0 v only v dr i out = 100 ma, (note 7) v dr = v in ? v out , ( v out = ? 100 mv) ? 0.225 0.45 v i out = 150 ma, (note 7) v dr = v in ? v out , ( v out = ? 100 mv) ? 0.30 0.60 output load capacitance c o output capacitance for stability 2.2 ? ? f power supply ripple rejection psrr v in = 13.2 v, 0.5 v pp , 100 hz ? 60 ? db dt (reset delay time select) threshold voltage high low 2 ? ? ? ? 0.8 v v input current dt = 5 v ? ? 1.0 a ro, reset output reset threshold v rf v out decreasing 90 93 96 %v out reset threshold hysteresis v rhys ? 2.0 ? %v out ro output low v rl 10 k reset to out, v out = 4.5 v ? 0.2 0.4 v ro output high (out ? ro) v rh 10 k reset to gnd v out ? 0.4 v out ? 0.2 v out v reset reaction time t rr v out into uv to reset low 16 25 38 sec input voltage reset threshold v in_rt v in decreasing, v out > v rt ? 3.8 4.25 v reset delay with dt selection delay time out of reset ? 8 ms version ? 16 ms version ? 32 ms version ? 64 ms version ? 128 ms version t drx v out into regulation to ro high 5.0 10 20 40 80 8.0 16 32 64 128 11.5 23 46 92 184 msec 6. not production tested, guaranteed by design. 7. dropout at a given current level is defined as the voltage difference of v in to v out with v in decreasing until the output drops by 100 mv.
ncv8660 http://onsemi.com 5 typical operating characteristics 25 c ? 40 c 150 c figure 3. output voltage vs. temperature (out = 5 v) figure 4. output voltage vs. temperature (out = 3.3 v) 4.96 4.965 4.97 4.975 4.98 4.985 4.99 4.995 5.0 0 20 40 60 120 temperature ( c) output voltage (v) 150 c 25 c ? 40 c output current (ma) output voltage (v) 0 1 2 3 4 5 6 0 0.5 1 1.5 2 2.5 output voltage (v) input voltage (v) i out = 0 ma, 150 ma ? 40 ? 20 80 100 140 160 4.96 4.965 4.97 4.975 4.98 4.985 4.99 4.995 5.0 0 20 40 60 120 80 100 140 160 4.955 3 3.5 4 4.5 5 5.5 6 25 c ? 40 c 150 c 3.260 3.265 3.270 3.280 3.285 3.295 3.300 3.305 3.315 0 20 40 60 120 temperature ( c) output voltage (v) 150 c 25 c ? 40 c output current (ma) output voltage (v) 0 0.5 1.0 2.5 3.0 3.5 0 0.5 1 1.5 2 2.5 output voltage (v) input voltage (v) i out = 0 ma, 150 ma ? 40 ? 20 80 100 140 160 3.260 3.265 3.270 3.280 3.285 3.290 3.295 3.300 3.310 0 20 40 60 120 80 100 140 160 3.255 3 3.5 4 4.5 5 5.5 6 figure 5. output voltage vs. output current (out = 5 v) figure 6. output voltage vs. output current (out = 3.3 v) figure 7. output voltage vs. input voltage (r load = 51 k, i out = 100 a, out = 5 v) figure 8. output voltage vs. input voltage (r load = 51 k, i out = 100 a, out = 3.3 v) 3.275 3.290 3.310 3.275 3.305 1.5 2.0
ncv8660 http://onsemi.com 6 typical operating characteristics 310 320 330 340 350 360 370 380 temperature ( c) current limit (ma) figure 9. current limit vs. temperature v in = 13.2 v 0 100 200 300 400 500 600 dropout voltage (mv) output current (ma) figure 10. dropout voltage vs. output current 150 c 25 c ? 40 c 150 ma temperature ( c) figure 11. dropout voltage vs. temperature 0 20 40 60 120 ? 40 ? 20 80 100 140 160 0 25 50 75 150 100 125 0 20 40 60 120 ? 40 ? 20 80 100 140 160 0 100 200 300 400 500 600 dropout voltage (mv) 1 ma 10 ma 25 ma 50 ma 75 ma 100 ma 125 ma figure 12. quiescent current vs. input voltage input voltage (v) quiescent current ( a) 0 5 10 15 20 25 30 35 40 02 4 6 12 810 1416 i out = 0 ma temperature ( c) quiescent current ( a) figure 13. quiescent current vs. temperature 23.5 24 24.5 25 25.5 26 26.5 27 27.5 0 20 40 60 120 ? 40 ? 20 80 100 140 160 28 29 28.5 quiescent current ( a) output current (ma) figure 14. quiescent current vs. output current 0 5 10 15 20 25 30 35 150 c 25 c ? 40 c 0 20 40 60 120 80 100 140 160
ncv8660 http://onsemi.com 7 typical operating characteristics figure 15. load transient (v in = 13.2 v, out = 5 v) figure 16. line transient (out = 5 v) c out = 2.2 f i out = 150 ma out in figure 17. load transient (v in = 13.2 v, out = 3.3 v) figure 18. line transient (out = 3.3 v)
ncv8660 http://onsemi.com 8 typical operating characteristics figure 19. ripple rejection vs. frequency (v in = 13.2 v, i out = 100 a) frequency figure 20. ripple rejection vs. frequency (v in = 13.2 v, i out = 150 ma) esr ( ) output current (ma) figure 21. output capacitor esr vs. output current (out = 5 v) 0.01 0.1 1 10 100 1000 10000 125 c 25 c ? 40 c 0 20 40 60 120 80 100 140 160 unstable region v in = 13.2 v c load = 2.2 f stable region 0 10 20 30 40 50 60 70 80 mag (db) 10 100 1 k 10 k 100 k 1 m 10 m frequency 0 10 20 30 40 50 60 70 80 mag (db) 10 100 1 k 10 k 100 k 1 m 10 m v in = 13.2 v c out = 4.7 f i out = 100 a v in = 13.2 v c out = 4.7 f i out = 150 ma esr ( ) output current (ma) figure 22. output capacitor esr vs. output current (out = 3.3 v) 0.01 0.1 1 10 100 1000 10000 125 c ? 40 c 0 20 40 60 120 80 100 140 160 unstable region v in = 13.2 v c load = 2.2 f stable region figure 23. thermal shutdown vs. temperature 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 25 50 75 150 temperature ( c) output voltage (v) temperature decreasing 100 125 175 4.5 5.0 5.5 temperature increasing 25 c
ncv8660 http://onsemi.com 9 detailed operating description general the ncv8660 is a 5 v and 3.3 v linear regulator providing low drop ? out voltage for 150 ma at low quiescent current levels. also featured in this part is a reset output with selectable delay times. delay times are selectable via part selection and control through the delay time select (dt) pin. no pull ? up resistor is needed on the reset output (ro). pull ? up and pull ? down capability are included. only a small bypass capacitor on the input (in) supply pin and output (out) voltage pin are required for normal operation. thermal shutdown functionality protects the ic from damage caused from excessively high temperatures appearing on the ic. output voltage output stability is determined by the capacitor selected from out to gnd. the ncv8660 has been designed to work with low esr (equivalent series resistance) ceramic capacitors. the device is extremely stable using virtually any capacitor 2.2 f and above. reference the output capacitor stability graph in figure 21. the output capacitor value will affect overshoot during power ? up. a lower value capacitor will cause higher overshoot on the output. system evaluation should be performed with minimum loading for evaluation of overshoot. selection of process technology for the ncv8660 allows for low quiescent current independent of loading. quiescent current will remain flat across the entire range of loads providing a low quiescent current condition in standby and under heavy loads. this is highly beneficial to systems requiring microprocessor interrupts during standby mode as duty cycle and load changes have no impact on the standby current. reference figure 14 for quiescent current vs output current. current limit current limit is provided on out to protect the ic. the minimum specification is 205 ma. current limit is specified under two conditions (out = 96% x out nominal) and (out = 0 v). no fold ? back circuitry exists. any measured differences can be attributed to change in die temperature. the part may be operated up to 205 ma provided thermal die temperature is considered and is kept below 150 c. degradation of electrical parameters at this current is expected at these elevated levels. a reset (ro) will not occur with a load less than 205 ma. reset output a reset signal is provided on the reset output (ro) pin to provide feedback to the microprocessor of an out of regulation condition. this is in the form of a logic signal on ro. output (out) voltage conditions below the reset threshold cause ro to go low. the ro integrity is maintained down to out = 1.0 v. the reset output (ro) circuitry includes an active internal pullup to the output (out) as shown in figure 24. no external pullup is neccessary. figure 24. reset output circuitry out ro reset control signal
ncv8660 http://onsemi.com 10 in out ro reset delay time reset threshold plus hysteresis thermal shutdown voltage dip at input secondary spike overload at output reset reaction time t t t out reset threshold plus hysteresis out reset threshold figure 25. reset timing thermal shutdown minus thermal hysteresis reset delay time reset delay time t < reset reaction time during power ? up (or restoring out voltage from a reset event), the out voltage must be maintained above the reset threshold for the reset delay time before ro goes high. the time for reset delay is determined by the choice of ic and the state of the dt pin. reset delay time select selection of the ncv8660 device and the state of the dt pin determines the available reset delay times. the part is designed for use with dt tied to ground or out, but may be controlled by any logic signal which provides a threshold between 0.8 v and 2 v. the default condition for an open dt pin is the slower reset time (dt = gnd condition). times are in pairs and are highlighted in the chart below. consult factory for availability. dt=gnd dt=out reset time reset time ncv86601 8 ms 128 ms ncv86602 8 ms 32 ms ncv86603 16 ms 64 ms ncv86604 32 ms 128 ms the delay time select (dt) pin is logic level controlled and provides reset delay time per the chart. note the dt pin is sampled only when ro is low, and changes to the dt pin when ro is high will not effect the reset delay time. thermal shutdown when the die temperature exceeds the thermal shutdown threshold, a thermal shutdown event is detected out is turned off, and ro goes low. the ic will remain in this state until the die temperature moves below the shutdown threshold (175 c typical) minus the hysteresis factor (25 c typical). the output will then turn back on and ro will go high after the reset delay time.
ncv8660 http://onsemi.com 11 40 50 60 70 80 90 100 110 0 100 200 300 400 500 600 700 copper heat spreader area (mm 2 ) figure 26. r ja vs. pcb copper area (dpak) thetaja ( c/w) power curve with pcb 1 oz cu figure 27. transient thermal response (dpak) cu area = 645 mm 2 0.001 0.01 0.1 1 10 100 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 r(t), ( c/w) pulse time (sec) single pulse 0.01 0.02 0.05 0.1 0.2 0.5 psi tab ? a 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 theta ja curve max power (w) 80 90 110 120 140 150 170 180 0 100 200 300 400 500 600 700 copper heat spreader area (mm 2 ) figure 28. r ja vs. pcb copper area (soic ? 8 fused) thetaja ( c/w) power curve with pcb 1 oz cu 0.7 0.8 0.9 1.0 1.1 1.2 1.3 theta ja curve max power (w) figure 29. transient thermal response (soic ? 8 fused) cu area = 645 mm 2 0.001 0.01 0.1 1 10 100 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 r(t), ( c/w) pulse time (sec) single pulse 0.01 0.02 0.05 0.1 0.2 0.5 psi l ? a 160 130 100
ncv8660 http://onsemi.com 12 ordering information device output voltage reset delay time, dt to gnd reset delay time, dt to out package shipping ? ncv86601dt50rkg 5.0 v 8 ms 128 ms dpak (pb ? free) 2500 / tape & reel ncv86602dt50rkg 8 ms 32 ms ncv86603dt50rkg 16 ms 64 ms ncv86604dt50rkg 32 ms 128 ms ncv86601d50g 8 ms 128 ms soic ? 8 fused (pb ? free) 98 units / rail ncv86601d50r2g 8 ms 128 ms 2500 / tape & reel ncv86602d50r2g 8 ms 32 ms ncv86603d50r2g 16 ms 64 ms ncv86604d50r2g 32 ms 128 ms ncv86601dt33rkg 3.3 v 8 ms 128 ms dpak (pb ? free) 2500 / tape & reel ncv86602dt33rkg 8 ms 32 ms ncv86603dt33rkg 16 ms 64 ms ncv86604dt33rkg 32 ms 128 ms ncv86601d33r2g 8 ms 128 ms soic ? 8 fused (pb ? free) 2500 / tape & reel ncv86602d33r2g 8 ms 32 ms NCV86603D33R2G 16 ms 64 ms ncv86604d33r2g 32 ms 128 ms ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d.
ncv8660 http://onsemi.com 13 package dimensions d a k b r v s f l g 5 pl m 0.13 (0.005) t e c u j h ? t ? seating plane z dim min max min max millimeters inches a 0.235 0.245 5.97 6.22 b 0.250 0.265 6.35 6.73 c 0.086 0.094 2.19 2.38 d 0.020 0.028 0.51 0.71 e 0.018 0.023 0.46 0.58 f 0.024 0.032 0.61 0.81 g 0.180 bsc 4.56 bsc h 0.034 0.040 0.87 1.01 j 0.018 0.023 0.46 0.58 k 0.102 0.114 2.60 2.89 l 0.045 bsc 1.14 bsc r 0.170 0.190 4.32 4.83 s 0.025 0.040 0.63 1.01 u 0.020 ??? 0.51 ??? v 0.035 0.050 0.89 1.27 z 0.155 0.170 3.93 4.32 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. r1 0.185 0.210 4.70 5.33 r1 1234 5 dpak 5, center lead crop dt suffix case 175aa ? 01 issue a 6.4 0.252 0.8 0.031 10.6 0.417 5.8 0.228 scale 4:1 mm inches 0.34 0.013 5.36 0.217 2.2 0.086 soldering footprint* *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d.
ncv8660 http://onsemi.com 14 package dimensions soic ? 8 nb case 751 ? 07 issue aj seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751 ? 01 thru 751 ? 06 are obsolete. new standard is 751 ? 07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ? x ? ? y ? g m y m 0.25 (0.010) ? z ? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 ncv8660/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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